`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/10 13:20:35
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module ALU(
    input [15:0]x,
    input [15:0]y,  // 16-bit inputs
    input zx, // zero the x input?
    input nx, // negate the x input?
    input zy, // zero the y input?
    input ny, // negate the y input?
    input f,  // compute out = x + y (if 1) or x & y (if 0)
    input no, // negate the out output?

    output [15:0]out, // 16-bit output
    output zr, // 1 if (out == 0), 0 otherwise
    output ng // 1 if (out < 0),  0 otherwise

  );

  logic [15:0] x1, x2;
  logic [15:0] y1, y2;
  logic [15:0] output1, output2;

  assign x1 = (zx == 1) ? 0 : x;
  assign x2 = (nx == 1) ? ~x1 : x1;

  assign y1 = (zy == 1) ? 0 : y;
  assign y2 = (ny == 1) ? ~y1 : y1;

  assign output1 = (f == 1) ? (x2 + y2) : (x2 & y2);
  assign output2 = (no == 1) ? ~output1 : output1;

  assign out = output2;
  assign zr = (output2 == 0);       // 0
  assign ng = (output2[15] == 1);   // 符号位

endmodule
